The Fundamental Design

ARM and RISC-V represent not just competing architectures, but competing philosophies of computing evolution:

ARM :

• Evolutionary Refinement: Each generation (Cortex-M0-M3-M4-M7-M85) builds upon proven foundations
• Complexity Management: Thumb-2 instruction encoding (mixed 16/32-bit) achieves code density through decoder complexity
• Legacy as Asset: ARMv7-M compatibility ensures binary longevity but carries microarchitectural baggage
• Unified Memory Model: Hierarchical privilege modes (Thread/Handler, EL0-EL3) with hardware-enforced security boundaries

RISC-V :

• Modular Deconstruction: Base ISA + Optional Extensions (I, M, A, F, D, C, V) = pick your complexity
• Simplicity Through Elimination: Fixed 32-bit encoding, regular field placement, minimal base instruction count
• Clean-Slate Design: No backward compatibility burden enables novel microarchitectural optimizations
• Radical Flexibility: Custom instruction extensions allow hardware-software co-design at unprecedented granularity

Register Set Architecture

ARM :

• 16 general-purpose registers: (r0-r12, SP, LR, PC)
• Hardware banking: Separate SP/LR for Handler Mode enables 12-cycle interrupt latency
• Auto-stacking: Hardware saves R0-R3, R12, LR, PC, PSR on interrupt entry
• Special registers: CONTROL, PRIMASK, FAULTMASK, BASEPRI for system control
• Dedicated return address: LR (R14) stores exception returns with special encoding

RISC-V :

• 32 general-purpose integer registers (x0-x31) + optional 32 FP registers
• Fixed roles: x0 hardwired to zero, x1=ra, x2=sp, x8=fp (by convention)
• No hardware stacking: Software manages context saving (flexibility vs overhead)
• CSRs (Control/Status Registers): Machine mode registers for system control
• Clean separation: No implicit register usage, but more save/restore overhead

Trade-off: ARM = faster context switches, RISC-V = simpler decode, more registers

Pipeline Architecture

ARM :

• M0/M0+: 2-stage (Fetch+Execute) – minimal power
• M3/M4: 3-stage + branch speculation – performance/power balance
• M7: 6-stage dual-issue + caches – high performance
• Deterministic interrupt handling: Pre-emption points carefully designed
• Branch shadow: 2-3 cycle penalty but good prediction in M4/M7

RISC-V :

• No prescribed pipeline: Implement 2-stage to 15+ stages
• Design freedom: Choose your own depth, bypassing, hazard detection
• Interrupt complexity: Async interrupts can be challenging in deep pipelines
• Simple decode: Regular instruction format simplifies early stages
• Custom extension hazard: Adding instructions requires pipeline modifications

Trade-off: ARM = proven, power-optimized pipelines; RISC-V = design freedom but you own the complexity

Addressing Modes

ARM :

• 9+ addressing modes: Immediate, register, scaled register, pre/post-indexed
• Load/store multiple: LDM/STM for stack operations (density advantage)
• PC-relative loads: Efficient constant pools and position-independent code
• Complex but efficient: Single instruction does load+pointer update

RISC-V :

• One primary mode: Base register + 12-bit immediate offset
• No load/store multiple: Software manages stack frames
• AUIPC instruction: For building 32-bit addresses (two instructions)
• Regularity: Simple decode, but more instructions for complex memory ops

Trade-off: ARM = better code density (15-30% smaller), RISC-V = simpler hardware

Operating/Privilege Modes

ARM :

• Cortex-M: Thread Mode (user) + Handler Mode (exceptions)
• TrustZone-M: Secure vs Non-secure worlds (hardware isolated)
• Cortex-A: EL0-EL3 (User, OS, Hypervisor, Secure Monitor)
• Hardware-managed transitions: Automatic stacking, mode switching
• Memory Protection: MPU (M-profile) or MMU (A-profile)

RISC-V :

• M-mode (Machine): Always present, highest privilege
• Optional S/U modes: Supervisor (OS) and User modes
• PMP (Physical Memory Protection): Simple memory protection scheme
• Custom privilege: Can implement your own security model
• Software-managed: More control, more responsibility

Trade-off: ARM = turnkey security models; RISC-V = design your own security architecture

Critical Performance Differences

Interrupt Latency (Real-Time) :

• ARM Cortex-M4: 12 cycles guaranteed with tail-chaining
• RISC-V typical: 20+ cycles (depends heavily on implementation)
• Determinism: ARM’s hardware stacking provides consistent timing

Code Density :

• Thumb-2: Mixed 16/32-bit provides excellent density
• RISC-V with C-extension: 16-bit compressed helps but still trails ARM
• Flash cost impact: RISC-V often needs 15-30% more flash → higher BOM cost

Power Efficiency :

• ARM: Fine-grained clock gating per pipeline stage
• RISC-V: Depends on implementation quality
• Active power: Comparable in similar implementations
• Sleep power: ARM has sophisticated sleep modes (WIC, retention)

“Based on this, when would you choose ARM and when would you pick RISC-V for your next project?”